Data processing devices sometimes include more than one clock domain, whereby different clock signals are applied to each clock domain, and the logic elements in each clock domain are synchronized to the clock applied to that domain. Transfer of data between two clock domains can be problematic when the clock signals associated with the clock domains have an uncertain frequency or phase relationship. Synchronizer logic can be interposed between the clock domains to facilitate data transfer, but can render the timing of data transfer indeterminate, thereby increasing the difficulty in testing the data processing device. Moreover, the synchronizer logic can consume an undesirable amount of die area, and also increase latency in the data transfer, reducing performance of the data processing device. Accordingly, an improved method and device for transferring data between clock domains would be useful.